The scaling of VLSI circuits is a constant effort. With circuits becoming smaller and faster, device driving current improvement becomes more important. Device current is closely related to gate length, gate capacitance, and carrier mobility. Shortening poly-gate length, increasing gate capacitance and increasing carrier mobility can improve the device current performance. Gate length reduction is an on-going effort in order to shrink circuit size. Increasing gate capacitance has also been achieved by efforts such as reducing the gate dielectric thickness, increasing the gate dielectric constant, and the like. In order to further improve device current, enhancing carrier mobility has also been explored.
Among efforts made to enhance carrier mobility, forming a stressed silicon channel is a known practice. Stress can enhance bulk electron and hole mobility. The performance of a CMOS transistor can be enhanced through a stressed-surface channel. This technique allows performance to be improved at a constant gate length, without adding complexity to circuit fabrication or design.
When silicon is placed under stress, the electron mobility is dramatically increased. Stress can also be applied to the channel region by forming a stress-inducing contact etch stop layer (CESL) over the transistor. When such a contact etch stop layer is deposited, due to the lattice spacing mismatch between the CESL and the underlying layer, a stress develops to match the lattice spacing.
The stress may have components parallel to the transistor channel and parallel to the transistor width direction. Research has revealed that a CESL that induces a tensile stress field in channel length direction can improve NMOS performance, and compressive stress can improve pMOS performance. In order to increase the beneficial effects and reduce the detrimental effects, it is desired that the tensile stress in the channel length direction be increased for nMOS transistors, and the compressive stress in the channel length direction be increased for pMOS transistors.
FIG. 1 illustrates a conventional NMOS transistor 1. Shallow trench isolations (STI) 4 are formed in the neighborhood of CMOS transistor 1. STIs 4 typically generate a compressive stress to the channel region of the transistor 1. This reduces the carrier mobility and hence degrades the device performance for NMOS transistors. Attempts are made to reduce the detrimental effect of the STIs 4. FIG. 2 illustrates one such attempt. The gate structure comprises a dielectric 10, a gate electrode 12 and gate spacers 14. STIs 4 are recessed below the surface of the substrate 2. The removal of the STI material at opposite ends of the device channel 16 eliminates the compressive force caused by the STI material. Silicides 8 are then formed. Since recessing the STIs 4 exposes the silicon substrate 2 at the sidewall 11 of the substrate 2, a silicide penetration 13 is formed on the sidewalls 11 of the STI recesses. The penetrations 13 cause a leakage current and therefore degrade the device performance. Typically, for CMOS transistors with wide junctions (the distance L between STIs 4 is great), there is less of a silicide penetration problem. When the devices are scaled down and the junctions are small, however, the penetration problem is more severe. Therefore, a method is needed for controlling the stress applied by STI without incurring a silicide penetration.